1. Field of the Invention
The present invention is related to a charging circuit, and particularly to a charging circuit with an application system capable of preventing from the circuit being frequently turned on and off.
2. Brief Description of the Related Art
The application of the power supply circuit employed in the field of the power generation with the solar energy usually provides a charging circuit to charge the battery for storing the superfluous electric power generated from the solar energy. When the generated power is insufficient at night or on the cloudy day, the stored power can be supplied to the load to achieve the purpose of power regulation.
Please referring to FIG. 1, the conventional charging circuit application system is illustrated. It can be seen in FIG. 1 that the charging circuit utilizes the output voltage VC of the comparator 14, which connects with the gate of the PMOS field effect transistor 12, to control if the PMOS field effect transistor 12 is in a state of being turned on to attain the purpose of controlling the charging power source 11 charging the battery 13. When the voltage VIN of the charging power source 11 gradually increases as shown in FIG. 2 to a state of the voltage difference V1-B between the source voltage VI and the drain voltage VB of the PMOS field effect transistor 12 being higher than the preset upper limit voltage VRT, the PMOS field effect transistor 12 is controlled by the output voltage VC of the comparator 14 to be turned on and start charging.
Meanwhile, the voltage divisions of the wire resistors 15, 16 allow the voltage difference V1-B entering the two input ends of the comparator 14 drops. Assume the resistance of the respective resistor 15, 16 is RWIRE, and the turning-on resistance of the PMOS field effect transistor 12 is RCHG, then the voltage difference V1-B is expressed in the following equation (1):
                              V                      I            ⁢                          -                        ⁢            B                          =                              R            CHG                    ×                                                    V                IN                            -                              V                BAT                                                                    R                WIRE                            +                              R                CHG                            +                              R                WIRE                                                                        (        1        )            
When the voltage difference V1-B drops to the lower limit voltage VFT, PMOS field effect transistor 12 is turned off due to being controlled by the output voltage VC of the comparator 14. This unstable state continues till the condition of the following equation (2) is reached. Hence, the preceding circuit is deficient.
                              V          IN                >                                                                              R                  WIRE                                +                                  R                  CHG                                +                                  R                  WIRE                                                            R                CHG                                      ×                          V              FT                                +                      V            BAT                                              (        2        )            